//////////////////////////////////////////////////////////////////////
////                                                              ////
////  sys_reset.v                                                 ////
////                                                              ////
////  This module generates the reset signal for the PPC at the   ////
////  request of the PC host.                                     ////
////                                                              ////
////  This file is part of the "PICO" project                     ////
////  http://www.picocomputing.com                                ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2004, Pico Computing, Inc.                     ////
//// http://www.picocomputing.com                                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////////////////////////////////////////////////////////////////////DH

`include "PicoDefines.v"
/*  The reset sequence involves a series of subordinate resets
  which is embodied in a separate core. This module generates the
  sys_rst signal after receiving a command over the PCMCIA bus:
      port[0x0C] = 0xDF
 This logic generates a high for DELAY_SIZE clocks and then drops to zero on sys_rst.
*/
module SysReset(clk, addr, din, dout, read, write, sys_rst, dcms_locked);

input  clk;	//opb_clock 100 Mhz
input  [`PCMCIA_ADR_LINES-1:1] addr;
input  [15:0] din;
output [15:0] dout;
input  read;
input  write;
input  dcms_locked;
output sys_rst;  //active high reset signal

wire master_reset;
wire startup_sys_rst;

//PCMCIA access is slow. Master_reset will be asserted for at least 100 nS.
assign master_reset  = ({addr[`PCMCIA_ADR_LINES-1:1],1'b0} == `PICOPORT_RESET_PPC) && 
                        write &&
							  (din[7:0] == `PPC_RST_PASSWORD); 
							  
SRL16 rst_delay(.Q(startup_sys_rst), .A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(clk && dcms_locked), .D(1'b0));
defparam rst_delay.INIT = 16'h7FFF; //holds reset high for 15 clocks.

assign sys_rst = startup_sys_rst || master_reset;

endmodule
